THE GLOBAL MARKET FOR EQUIPMENT AND MATERIALS FOR IC MANUFACTURING
出 版 商：The Information Network
出版日期：2016/10/01
價 格：
USD 4,995 (Single-User License)
Chapter 1 Introduction 1-1
Chapter 2 Low-K Dielectric Issues and Trends 2-1
2.1 Introduction 2-1
2.2 Ideal Dielectric 2-2
2.3 Types of Low-K Dielectrics 2-5
2.3.1 FSG 2-5
2.3.2 HSQ 2-7
2.3.3 Nanoporous Silica 2-8
2.3.4 Spin-on Polymers 2-9
2.3.5 BCB 2-17
2.3.6 Flowfill 2-17
2.3.7 CVD 2-18
2.3.8 AF4 2-21
2.3.9 PTFE 2-23
2.4 Summary 2-24
2.4.1 Processing Issues 2-24
2.4.2 Integration Issues 2-31
Chapter 3 Lithography Issues And Trends 3-1
3.1 Optical Systems 3-1
3.1.1 Introduction 3-1
3.1.2 Step-and-Repeat Aligners 3-8
3.1.3 Deep Ultraviolet (DUV) 3-11
3.2 EUV 3-18
3.5 Nano-Imprint Lithography 3-23
3.4 X-Ray Lithography 3-28
3.3 Electron Beam Lithography 3-34
3.4 Ion Beam Lithography 3-38
Chapter 4 CMP Issues and Trends 4-1
4.1 Need for Planarity 4-1
4.1.1 Lithography 4-4
4.1.2 Deposition 4-6
4.1.3 Etching 4-10
4.2 Applications 4-13
4.2.1 Dielectrics 4-13
4.2.2 Metals 4-15
4.3 Planarization Techniques 4-17
4.3.1 Local Planarization 4-17
4.3.1.1 Deposition-Etchback 4-17
4.3.1.2 ECR 4-19
4.3.1.3 Oxide Reflow 4-19
4.3.1.4 Spin-on-Glass 4-20
4.3.1.5 TEOS-Ozone 4-20
4.3.1.6 Laser 4-21
4.3.2 Global Planarization 4-22
4.3.2.1 Polymer 4-22
4.3.2.2 Polyimide 4-24
4.3.2.3 Isotropic Etch 4-24
4.3.2.4 Spin Etch Planarization 4-25
4.3.2.5 Electropolishing 4-26
4.4 Chemical Mechanical Polishing (CMP) 4-28
4.4.1 Background 4-33
4.4.2 Research Efforts 4-34
4.4.3 Advantages and Disadvantages 4-33
4.4.4 Process Parameters 4-37
4.4.4.1 STI Planarization 4-38
4.4.4.2 Copper CMP 4-43
4.4.4.3 Low-K Integration 4-57
4.4.4.4 Defect Density 4-65
4.4.4.5 Metrology 4-67
4.4.5 Device Processing Parameters 4-80
4.4.5.1 Memory Devices 4-80
4.4.5.2 Logic Devices 4-81
Chapter 5 Factory Automation Issues and Trends 5-1
5.1 Introduction 5-1
5.2 Elements of Automation 5-4
5.2.1 Tool Automation 5-4
5.2.2 Intrabay Automation 5-7
5.2.3 Interbay Automation 5-9
5.2.4 Material-Control System 5-11
5.3 Flexible Automation 5-13
5.4 Reliability 5-15
5.5 Tool Issues and Trends 5-17
5.5.1 Flexible Tool Interface 5-17
5.5.2 Vacuum Robotics 5-36
5.5.3 AGV 5-45
5.5.4 Robot Control Systems 6-49
5.5.5 300-mm Wafer Transport 5-50
5.5.6 Mini-Environments and Cleanroom Issues 5-53
5.6 E-Manufacturing 5-57
Chapter 6 Thin film Deposition Issues and Trends 6-1
6.1 Physical Vapor Deposition 6-1
6.1.1 Sputtering Technology 6-2
6.1.2 Plasma Technology 6-5
6.1.3 Reactor Designs 6-14
6.1.3.1 Long-Throw Deposition 6-14
6.1.3.2 Collimated Sputter Deposition 6-16
6.1.3.3 Showerhead Deposition 6-18
6.1.3.4 Ionized PVD 6-22
6.1.4 Semiconductor Processing 6-28
6.1.4.1 Feature Patterning 6-28
6.1.4.2 Gap Fill 6-31
6.2 Chemical Vapor Deposition (CVD) Techniques 6-34
6.2.1 APCVD 6-35
6.2.2 LPCVD 6-39
6.2.3 PECVD 6-42
6.2.4 HDPCVD 6-46
6.2.5 ALD 6-52
6.2.5.1 Gate Dielectrics 6-55
6.2.5.2 Gate Electrodes 6-56
6.2.5.3 Metal Interconnects 6-57
6.2.5.4 Diffusion Barriers 6-57
6.2.5.5 DRAM 6-60
Chapter 7 Plasma Etching Issues and Trends 7-1
7.1 Introduction 7-1
7.2 Processing Issues 7-14
7.2.1 Chlorine Versus Fluorine Processes 7-19
7.2.2 Multilevel Structures 7-32
7.2.3 New Metallization Materials 7-39
7.2.4 GaAs Processing 7-47
7.3 Plasma Stripping 7-48
7.3.1 Photoresist Stripping 7-48
7.3.2 Low-K Removal 7-69
Chapter 8 Chemicals and Materials Issues and Trends 8-1
8.1 Technology Issues 8-1
8.1.1 Acids and Solvents 8-1
8.1.2 Resists 8-5
8.2 Purity Requirements 8-14
8.2.1 Purification Methods 8-14
8.2.1.1 Trends For Purity - Trace Elements 8-15
8.2.2 Particulates 8-16
8.2.1.1 Effects on Yield 8-16
8.2.1.2 Particulate Removal Techniques 8-22
8.2.1.3 Particle Monitoring 8-23
8.3 Chemical Management 8-24
8.3.1 Introduction 8-24
8.3.2 Chemical Usage Reduction 8-26
8.4 Gases 8-30
8.4.1 Requirements 8-30
8.4.1.1 Purification Alternatives 8-30
8.4.2 Particulate Considerations 8-34
8.4.2.1 Particle Monitoring 8-34
8.4.2.2 Filtration Methods 8-36
8.4.3 Summary 8-40
8.5 Sputtering and Evaporation Materials 8-41
8.5.1 Technology Issues 8-41
8.5.2 Purity Requirements 8-51
Chapter 9 Metrology 9-1
9.1 Defect Review/Wafer Inspection 9-1
9.1.2 Defect Review 9-2
9.1.2.1 SEM Defect Review 9-3
9.1.2.2 Optical Defect Review 9-5
9.1.2.3 Other Defect Review 9-6
9.1.3 Patterned Wafer Inspection 9-8
9.1.3.1 E-Beam Patterned Wafer Inspection 9-9
9.1.3.2 Optical Patterned Wafer Inspection 9-12
9.1.4 Unpatterned Wafer Inspection 9-18
9.1.5 Macro-Defect Inspection 9-21
9.2 Thin Film Metrology 9-23
9.2.1 Metal Thin-Film Metrology 9-25
9.2.2 Non-Metal Thin-Film Metrology 9-32
9.2.3 Substrate Metrology 9-46
9.3 Lithography Metrology 9-49
9.3.1 Overlay 9-49
9.3.2 CD 9-54
9.3.3 Mask (Reticle) Metrology/Inspection 9-69
Chapter 10 Market Forecast 10-1
10.1 Market Drivers 10-1
10.1.1 Semiconductor Market 10-1
10.1.2 Technical Trends 10-3
10.1.3 Economic Trends 10-8
10.1.4 Geographic Trends 10-11
10.1.4.1 China 10-11
10.1.4.2 Asia 10-12
10.1.4.3 Europe 10-13
10.1.4.4 Japan 10-14
10.1.4.5 United States 10-15
10.2 Market Forecast Assumptions 10-16
10.3 Low-K Market 10-17
10.4 Lithography Market 10-22
10.5 CMP Market 10-26
10.5.1 CMP Polisher Market 10-26
10.5.2 CMP Slurry Market 10-30
10.6 Factory Automation Market 10-33
10.7 Thin Film Deposition Market 10-41
10.7.1 Chemical Vapor Deposition Market 10-43
10.7.2 Physical Vapor Deposition Market 10-47
10.8 Plasma Etching Market 10-50
10.9 Chemical and Materials Market 10-54
10.9.1 Forecast by Chemical and Material 10-54
10.9.2 Market Shares 10-57
10.10 Metrology Market 10-61
FIGURES
2.1 Interconnect Delay for Copper/Low-K 2-3
3.1 Lithography Options For MPUs/DRAMs 3-6
3.2 Lithography Options For Flash 3-7
3.3 Illustration of Stepper Exposure System 3-9
3.4 Lens Arrangement For Submicron Features 3-14
3.5 Excimer Laser Evolution 3-15
3.6 EUV Lithography 3-18
3.7 Thermoplastic Nanoimprint Lithography Process 3-23
3.8 Step And Flash Nanoimprint Lithography Process 3-25
3.9 Illustration of X-Ray Lithography 3-30
3.10 Schematic Of Scalpel Electron Beam System 3-34
3.11 Multi-Source E-Beam Lithography 3-36
3.12 Ion Projection Lithography System 3-39
4.1 Planarization Lengths of Various Methods 4-18
4.2 Normalized Removal Rates 4-29
4.3 Reduced Complexity With Copper 4-45
4.4 Copper Loss From CMP 4-50
4.5 CMP Copper Process Technologies 4-52
4.6 CMP Performance Improvements 4-54
4.7 Polish Endpoint Control 4-78
5.1 Material-Control System 5-12
5.2 Traditional and Flexible Automated Material Handling System 5-14
5.3 Overhead Monorail Delivery - Cassette in Box, Cassette in SMIF Pod 5-20
SMIF Pod 5-20
5.4 Stocker Design and Interfaces 5-55
5.5 Layout Of a 45nm 300mm Fab 5-61
5.6 Interfaces To Factory Automation Systems 5-65
6.1 Schematic Of Sputtering System 6-3
6.2 Magnetron Sputtering Design 6-9
6.3 Showerhead Reactor Design 6-19
6.4 Ionized PVD 6-24
6.5 APCVD Reactor 6-36
6.6 Tube CVD Reactor 6-40
6.7 HDPCVD Reactor 6-50
6.8 ALD Versus PVD Copper Barrier 6-59
7.1 Various Enhanced Designs (a) Helicon, (b) Multiple ECR, (c) Helical Resonator 7-4
7.2 Schematic of Inductively Coupled Plasma Source 7-6
7.3 Schematic of the HRe Source 7-9
7.4 Schematic of the Dipole Magnet Source 7-10
7.5 Schematic of Chemical Downstream Etch 7-11
7.6 Silicon Trench Structure 7-21
7.7 Dual Damascene Dielectric Etch Approaches 7-35
8.1 Relationship Between Device Yield and Particles 8-18
8.2 Relationship Between Die Yield and Chip Size 8-20
8.3 Chemical Management Services Tasks 8-25
8.4 ITRS Roadmap 8-44
8.5 Gate-Last Approach 8-49
8.6 Gate-First Approach 8-50
9.1 Spectroscopic Ellipsometry Diagram 9-39
9.2 ITRS Overlay Technology Roadmap 9-51
9.3 Illustration Of 3D Structure 9-57
9.4 ITRS Metrology Roadmap 9-63
9.5 Illustration Of 3D Structure 9-68
10.1 Low-K Deposition Market Shares 10-22
10.2 Worldwide Lithography Market Shares 10-24
10.3 Semiconductor Equipment Utilization 10-35
10.4 Market Shares of Automated Wafer Transfer Suppliers 10-40
10.5 Worldwide MCVD Market Shares 10-45
10.6 Worldwide DCVD Market Shares 10-46
10.7 Worldwide PVD Market Shares 10-49
10.8 Worldwide Market Shares for Dry Etch Equipment 10-52
10.9 Distribution of Etch Sales by Type 10-53
10.10 Worldwide Market Shares of Liquid Chemical Suppliers 10-61
10.11 Worldwide Market Shares of Photoresist Suppliers 10-62
10.12 Worldwide Market Shares of Silicon Wafer Suppliers 10-63
10.13 Worldwide Market Shares of Gas Suppliers 10-64
10.14 Total Metrology Market Forecast 10-67
10.15 Total Metrology Market Shares 10-69
TABLES
2.1 Low-K Material Requirements 2-4
2.2 Low-K Materials 2-6
3.1 Wavelength “Generations” 3-5
3.2 Characteristics of X-Ray Systems 3-29
4.1 Levels of Integration of Dynamic Rams 4-2
4.2 Interconnect Levels of Logic Device 4-3
4.3 Typical Process Specifications 4-11
4.4 Organic Polymers for IMD Applications 4-21
4.5 CMP Process Variables 4-29
4.7 Optimized CMP and Post-CMP Clean Parameters 4-37
4.8 Interconnect Materials by Segment 4-46
5.1 Evolution Of Factory Metrics 5-58
7.1 Silicon Wafer Usage 7-2
7.2 Plasma Source Comparison 7-12
7.3 Typical Process Specifications 7-18
7.4 Dry Resist Stripping Systems 7-52
8.1 Common Wafer Processing Chemicals 8-2
8.2 Photoresist Stripping Solutions 8-10
8.3 Potential Hazards of Processing Gases 8-35
9.1 Comparison Of White-Light With Multiple-Angle Laser Ellipsometry 9-32
10.1 Worldwide Capital Spending 10-9
10.2 Worldwide GDP 10-10
10.3 Worldwide Market Forecast Low-K Market 10-18
10.4 Worldwide Stepper Market 10-23
10.5 Worldwide CMP Polisher Market 10-27
10.6 Worldwide CMP Market Shares 10-29
10.7 Worldwide CMP Slurry Market 10-31
10.8 Worldwide Forecast of Automated Transfer Tools 10-37
10.9 Worldwide CVD Market Forecast 10-44
10.10 Worldwide PVD Market Forecast 10-48
10.11 Worldwide Market Forecast of Plasma Etching Systems 10-51
10.12 Worldwide Forecast of Chemicals and Materials 10-55
10.13 Total Metrology Market Forecast 10-66
Chapter 2 Low-K Dielectric Issues and Trends 2-1
2.1 Introduction 2-1
2.2 Ideal Dielectric 2-2
2.3 Types of Low-K Dielectrics 2-5
2.3.1 FSG 2-5
2.3.2 HSQ 2-7
2.3.3 Nanoporous Silica 2-8
2.3.4 Spin-on Polymers 2-9
2.3.5 BCB 2-17
2.3.6 Flowfill 2-17
2.3.7 CVD 2-18
2.3.8 AF4 2-21
2.3.9 PTFE 2-23
2.4 Summary 2-24
2.4.1 Processing Issues 2-24
2.4.2 Integration Issues 2-31
Chapter 3 Lithography Issues And Trends 3-1
3.1 Optical Systems 3-1
3.1.1 Introduction 3-1
3.1.2 Step-and-Repeat Aligners 3-8
3.1.3 Deep Ultraviolet (DUV) 3-11
3.2 EUV 3-18
3.5 Nano-Imprint Lithography 3-23
3.4 X-Ray Lithography 3-28
3.3 Electron Beam Lithography 3-34
3.4 Ion Beam Lithography 3-38
Chapter 4 CMP Issues and Trends 4-1
4.1 Need for Planarity 4-1
4.1.1 Lithography 4-4
4.1.2 Deposition 4-6
4.1.3 Etching 4-10
4.2 Applications 4-13
4.2.1 Dielectrics 4-13
4.2.2 Metals 4-15
4.3 Planarization Techniques 4-17
4.3.1 Local Planarization 4-17
4.3.1.1 Deposition-Etchback 4-17
4.3.1.2 ECR 4-19
4.3.1.3 Oxide Reflow 4-19
4.3.1.4 Spin-on-Glass 4-20
4.3.1.5 TEOS-Ozone 4-20
4.3.1.6 Laser 4-21
4.3.2 Global Planarization 4-22
4.3.2.1 Polymer 4-22
4.3.2.2 Polyimide 4-24
4.3.2.3 Isotropic Etch 4-24
4.3.2.4 Spin Etch Planarization 4-25
4.3.2.5 Electropolishing 4-26
4.4 Chemical Mechanical Polishing (CMP) 4-28
4.4.1 Background 4-33
4.4.2 Research Efforts 4-34
4.4.3 Advantages and Disadvantages 4-33
4.4.4 Process Parameters 4-37
4.4.4.1 STI Planarization 4-38
4.4.4.2 Copper CMP 4-43
4.4.4.3 Low-K Integration 4-57
4.4.4.4 Defect Density 4-65
4.4.4.5 Metrology 4-67
4.4.5 Device Processing Parameters 4-80
4.4.5.1 Memory Devices 4-80
4.4.5.2 Logic Devices 4-81
Chapter 5 Factory Automation Issues and Trends 5-1
5.1 Introduction 5-1
5.2 Elements of Automation 5-4
5.2.1 Tool Automation 5-4
5.2.2 Intrabay Automation 5-7
5.2.3 Interbay Automation 5-9
5.2.4 Material-Control System 5-11
5.3 Flexible Automation 5-13
5.4 Reliability 5-15
5.5 Tool Issues and Trends 5-17
5.5.1 Flexible Tool Interface 5-17
5.5.2 Vacuum Robotics 5-36
5.5.3 AGV 5-45
5.5.4 Robot Control Systems 6-49
5.5.5 300-mm Wafer Transport 5-50
5.5.6 Mini-Environments and Cleanroom Issues 5-53
5.6 E-Manufacturing 5-57
Chapter 6 Thin film Deposition Issues and Trends 6-1
6.1 Physical Vapor Deposition 6-1
6.1.1 Sputtering Technology 6-2
6.1.2 Plasma Technology 6-5
6.1.3 Reactor Designs 6-14
6.1.3.1 Long-Throw Deposition 6-14
6.1.3.2 Collimated Sputter Deposition 6-16
6.1.3.3 Showerhead Deposition 6-18
6.1.3.4 Ionized PVD 6-22
6.1.4 Semiconductor Processing 6-28
6.1.4.1 Feature Patterning 6-28
6.1.4.2 Gap Fill 6-31
6.2 Chemical Vapor Deposition (CVD) Techniques 6-34
6.2.1 APCVD 6-35
6.2.2 LPCVD 6-39
6.2.3 PECVD 6-42
6.2.4 HDPCVD 6-46
6.2.5 ALD 6-52
6.2.5.1 Gate Dielectrics 6-55
6.2.5.2 Gate Electrodes 6-56
6.2.5.3 Metal Interconnects 6-57
6.2.5.4 Diffusion Barriers 6-57
6.2.5.5 DRAM 6-60
Chapter 7 Plasma Etching Issues and Trends 7-1
7.1 Introduction 7-1
7.2 Processing Issues 7-14
7.2.1 Chlorine Versus Fluorine Processes 7-19
7.2.2 Multilevel Structures 7-32
7.2.3 New Metallization Materials 7-39
7.2.4 GaAs Processing 7-47
7.3 Plasma Stripping 7-48
7.3.1 Photoresist Stripping 7-48
7.3.2 Low-K Removal 7-69
Chapter 8 Chemicals and Materials Issues and Trends 8-1
8.1 Technology Issues 8-1
8.1.1 Acids and Solvents 8-1
8.1.2 Resists 8-5
8.2 Purity Requirements 8-14
8.2.1 Purification Methods 8-14
8.2.1.1 Trends For Purity - Trace Elements 8-15
8.2.2 Particulates 8-16
8.2.1.1 Effects on Yield 8-16
8.2.1.2 Particulate Removal Techniques 8-22
8.2.1.3 Particle Monitoring 8-23
8.3 Chemical Management 8-24
8.3.1 Introduction 8-24
8.3.2 Chemical Usage Reduction 8-26
8.4 Gases 8-30
8.4.1 Requirements 8-30
8.4.1.1 Purification Alternatives 8-30
8.4.2 Particulate Considerations 8-34
8.4.2.1 Particle Monitoring 8-34
8.4.2.2 Filtration Methods 8-36
8.4.3 Summary 8-40
8.5 Sputtering and Evaporation Materials 8-41
8.5.1 Technology Issues 8-41
8.5.2 Purity Requirements 8-51
Chapter 9 Metrology 9-1
9.1 Defect Review/Wafer Inspection 9-1
9.1.2 Defect Review 9-2
9.1.2.1 SEM Defect Review 9-3
9.1.2.2 Optical Defect Review 9-5
9.1.2.3 Other Defect Review 9-6
9.1.3 Patterned Wafer Inspection 9-8
9.1.3.1 E-Beam Patterned Wafer Inspection 9-9
9.1.3.2 Optical Patterned Wafer Inspection 9-12
9.1.4 Unpatterned Wafer Inspection 9-18
9.1.5 Macro-Defect Inspection 9-21
9.2 Thin Film Metrology 9-23
9.2.1 Metal Thin-Film Metrology 9-25
9.2.2 Non-Metal Thin-Film Metrology 9-32
9.2.3 Substrate Metrology 9-46
9.3 Lithography Metrology 9-49
9.3.1 Overlay 9-49
9.3.2 CD 9-54
9.3.3 Mask (Reticle) Metrology/Inspection 9-69
Chapter 10 Market Forecast 10-1
10.1 Market Drivers 10-1
10.1.1 Semiconductor Market 10-1
10.1.2 Technical Trends 10-3
10.1.3 Economic Trends 10-8
10.1.4 Geographic Trends 10-11
10.1.4.1 China 10-11
10.1.4.2 Asia 10-12
10.1.4.3 Europe 10-13
10.1.4.4 Japan 10-14
10.1.4.5 United States 10-15
10.2 Market Forecast Assumptions 10-16
10.3 Low-K Market 10-17
10.4 Lithography Market 10-22
10.5 CMP Market 10-26
10.5.1 CMP Polisher Market 10-26
10.5.2 CMP Slurry Market 10-30
10.6 Factory Automation Market 10-33
10.7 Thin Film Deposition Market 10-41
10.7.1 Chemical Vapor Deposition Market 10-43
10.7.2 Physical Vapor Deposition Market 10-47
10.8 Plasma Etching Market 10-50
10.9 Chemical and Materials Market 10-54
10.9.1 Forecast by Chemical and Material 10-54
10.9.2 Market Shares 10-57
10.10 Metrology Market 10-61
FIGURES
2.1 Interconnect Delay for Copper/Low-K 2-3
3.1 Lithography Options For MPUs/DRAMs 3-6
3.2 Lithography Options For Flash 3-7
3.3 Illustration of Stepper Exposure System 3-9
3.4 Lens Arrangement For Submicron Features 3-14
3.5 Excimer Laser Evolution 3-15
3.6 EUV Lithography 3-18
3.7 Thermoplastic Nanoimprint Lithography Process 3-23
3.8 Step And Flash Nanoimprint Lithography Process 3-25
3.9 Illustration of X-Ray Lithography 3-30
3.10 Schematic Of Scalpel Electron Beam System 3-34
3.11 Multi-Source E-Beam Lithography 3-36
3.12 Ion Projection Lithography System 3-39
4.1 Planarization Lengths of Various Methods 4-18
4.2 Normalized Removal Rates 4-29
4.3 Reduced Complexity With Copper 4-45
4.4 Copper Loss From CMP 4-50
4.5 CMP Copper Process Technologies 4-52
4.6 CMP Performance Improvements 4-54
4.7 Polish Endpoint Control 4-78
5.1 Material-Control System 5-12
5.2 Traditional and Flexible Automated Material Handling System 5-14
5.3 Overhead Monorail Delivery - Cassette in Box, Cassette in SMIF Pod 5-20
SMIF Pod 5-20
5.4 Stocker Design and Interfaces 5-55
5.5 Layout Of a 45nm 300mm Fab 5-61
5.6 Interfaces To Factory Automation Systems 5-65
6.1 Schematic Of Sputtering System 6-3
6.2 Magnetron Sputtering Design 6-9
6.3 Showerhead Reactor Design 6-19
6.4 Ionized PVD 6-24
6.5 APCVD Reactor 6-36
6.6 Tube CVD Reactor 6-40
6.7 HDPCVD Reactor 6-50
6.8 ALD Versus PVD Copper Barrier 6-59
7.1 Various Enhanced Designs (a) Helicon, (b) Multiple ECR, (c) Helical Resonator 7-4
7.2 Schematic of Inductively Coupled Plasma Source 7-6
7.3 Schematic of the HRe Source 7-9
7.4 Schematic of the Dipole Magnet Source 7-10
7.5 Schematic of Chemical Downstream Etch 7-11
7.6 Silicon Trench Structure 7-21
7.7 Dual Damascene Dielectric Etch Approaches 7-35
8.1 Relationship Between Device Yield and Particles 8-18
8.2 Relationship Between Die Yield and Chip Size 8-20
8.3 Chemical Management Services Tasks 8-25
8.4 ITRS Roadmap 8-44
8.5 Gate-Last Approach 8-49
8.6 Gate-First Approach 8-50
9.1 Spectroscopic Ellipsometry Diagram 9-39
9.2 ITRS Overlay Technology Roadmap 9-51
9.3 Illustration Of 3D Structure 9-57
9.4 ITRS Metrology Roadmap 9-63
9.5 Illustration Of 3D Structure 9-68
10.1 Low-K Deposition Market Shares 10-22
10.2 Worldwide Lithography Market Shares 10-24
10.3 Semiconductor Equipment Utilization 10-35
10.4 Market Shares of Automated Wafer Transfer Suppliers 10-40
10.5 Worldwide MCVD Market Shares 10-45
10.6 Worldwide DCVD Market Shares 10-46
10.7 Worldwide PVD Market Shares 10-49
10.8 Worldwide Market Shares for Dry Etch Equipment 10-52
10.9 Distribution of Etch Sales by Type 10-53
10.10 Worldwide Market Shares of Liquid Chemical Suppliers 10-61
10.11 Worldwide Market Shares of Photoresist Suppliers 10-62
10.12 Worldwide Market Shares of Silicon Wafer Suppliers 10-63
10.13 Worldwide Market Shares of Gas Suppliers 10-64
10.14 Total Metrology Market Forecast 10-67
10.15 Total Metrology Market Shares 10-69
TABLES
2.1 Low-K Material Requirements 2-4
2.2 Low-K Materials 2-6
3.1 Wavelength “Generations” 3-5
3.2 Characteristics of X-Ray Systems 3-29
4.1 Levels of Integration of Dynamic Rams 4-2
4.2 Interconnect Levels of Logic Device 4-3
4.3 Typical Process Specifications 4-11
4.4 Organic Polymers for IMD Applications 4-21
4.5 CMP Process Variables 4-29
4.7 Optimized CMP and Post-CMP Clean Parameters 4-37
4.8 Interconnect Materials by Segment 4-46
5.1 Evolution Of Factory Metrics 5-58
7.1 Silicon Wafer Usage 7-2
7.2 Plasma Source Comparison 7-12
7.3 Typical Process Specifications 7-18
7.4 Dry Resist Stripping Systems 7-52
8.1 Common Wafer Processing Chemicals 8-2
8.2 Photoresist Stripping Solutions 8-10
8.3 Potential Hazards of Processing Gases 8-35
9.1 Comparison Of White-Light With Multiple-Angle Laser Ellipsometry 9-32
10.1 Worldwide Capital Spending 10-9
10.2 Worldwide GDP 10-10
10.3 Worldwide Market Forecast Low-K Market 10-18
10.4 Worldwide Stepper Market 10-23
10.5 Worldwide CMP Polisher Market 10-27
10.6 Worldwide CMP Market Shares 10-29
10.7 Worldwide CMP Slurry Market 10-31
10.8 Worldwide Forecast of Automated Transfer Tools 10-37
10.9 Worldwide CVD Market Forecast 10-44
10.10 Worldwide PVD Market Forecast 10-48
10.11 Worldwide Market Forecast of Plasma Etching Systems 10-51
10.12 Worldwide Forecast of Chemicals and Materials 10-55
10.13 Total Metrology Market Forecast 10-66
